1. Field of the Invention
The invention relates to the field of three-dimensional integration of integrated circuits. In particular, the present invention relates to methods for manufacturing a through substrate via in semiconductor chips, and to semiconductor chips prepared for being provided with and/or being provided with such through substrate vias.
2. Description of the Related Technology
The semiconductor industry has been able to steadily reduce the cost per function and to increase the function density in integrated circuits over the last three decades. At the same time, the different abstraction levels separating semiconductor design and manufacturing have enabled efficient product design cycles and fast time-to-market. However, economical and technical issues may slow down the scaling effort beyond the 32 nm node.
FIG. 1 shows a prior art example of a CMOS device with a substrate 5, comprising a front-end-of-line 1 comprising active devices, for example transistors. On top there is a back-end-of-line 3 comprising a multi-layer of metal/dielectric. The back-end-of-line 3 comprises different metal levels, e.g. Cu or Al, labelled from M1 to Mn and isolated from each other by means of interlayer dielectric layers 15, and contacts or vias, labelled Via 1 to Via n, interconnecting the different metal levels M1 to Mn through the interlayer dielectric layers 15. The (electrical) connection between the front-end-of-line 1 and the metal levels, in particular metal one M1, in the back-end-of-line 3 is made by means of contacts 2.
For many applications different ICs, for example with different functionalities are connected with each other. Therefore, connections are made between the back-end-of-line parts 3 of the different ICs that are to be connected. In case of ICs that are positioned next to each other, connecting the back-end-of-line parts 3 of the different ICs can be done with long wiring.
To keep on reducing the cost per function, one possibility is to move to a three-dimensional (3D) stacking of integrated circuits (ICs). In this approach, devices are stacked on top of each other rather than next to each other. This reduces significantly the area that is used for the ICs and permits to extend the number of functions per area of the integrated device or system when compared to non-stacked ICs. Using 3D chip stacking, it is possible to extend the number of functions per area of the integrated device or system well beyond the near-term capabilities of traditional scaling. 3D strata are the individual device layers that build up the 3D system. These layers can be processed separately to be stacked later in the process flow. The 3D strata may be realized using advanced CMOS technology nodes but may also exploit a wide variety of device technologies to optimize system performance. Such heterogeneous 3D stacks may include, or consist of, e.g. CMOS, BiCMOS, different memory technologies and even MEMS, integrated passive layers and optical components like for example GaN (III-V).
Different product applications may require different 3D-interconnect technology solutions. In 3D technology these may be interconnect technologies at the package level, wafer level and/or foundry level. 3D stacking and interconnection technologies are mainly limited to the assembly techniques that realize 3D-interconnects at the packaging interconnects level. Technologies for through substrate via (TSV) connections are only emerging and not widely available for volume manufacturing. Depending on their TSV diameter and pitch capabilities, these technologies principally target to enable 3D interconnectivity at the IC bond-pad and IP-block level, as well as at the global, intermediate or even local level of the interconnect hierarchy. TSVs can be applied to single layer semiconductor devices, but also to substrates, stacked semiconductor devices or substrates . . . .
In literature, a wide variety of TSV integration schemes has been proposed. Most of these integration schemes described in literature include:                making of a deep hole in or through the substrate (typically using laser drilling, DRIE, . . . ),        isolation of the hole using an insulator or dielectric material (typically SiO2, SiN, polymers, . . . ),        application of conductive material or metallization into the via hole (typically Cu, W, but also Al, Au, Sn, poly-Si, . . . ).        
The TSV integration schemes can differ in terms of                the type of the substrates (Si, SOI, . . . ),        the position in the process flow for fabrication of the device where the TSV is processed (examples are before front-end-of-line (FEOL), after FEOL & before back-end-of-line (BEOL), after BEOL, after stacking, before/after thinning . . . ),        the way in which devices or substrates are stacked on top of each other and the way in which the TSV is interconnected to the next level in the stack (Oxide/oxide stacking in combination with a metallic interconnect, conductive polymer adhesive, Cu/Cu metal fusion, solder (microbump), Hybrid metal/dielectric bond, . . . ),        the side of the wafer from which the TSV hole is processed (Wafer/substrate front or wafer/substrate backside).        
The side of the wafer from which the TSV hole is processed is a major differentiator in complexity when applying the process e.g. to semiconductor devices.
As the before, FIG. 1 shows an example of a regular CMOS stack built-up with a multi-layer metal/dielectric back-end-of-line 3.
Often, TSVs 10 are processed from the device top side during back-end-of-line processing as illustrated in FIG. 2. In that case the TSV hole is etched or drilled during or after back-end-of-line processing at least through (part of) the multilayer back-end-of-line 3 being a layered stack containing a variety of materials (such as for example metals e.g. Cu, Al, . . . and dielectrics e.g. oxides, nitrides, carbides, . . . ). After processing the hole through the BEOL 3 layers, it needs to be further deepened to extend through the pre-metal dielectric layer (PMD) 13 and into the substrate 5, e.g. silicon substrate. In view of the number of materials the hole needs to be drilled or etched through (at least metal layers, ILD layers, PMD layers, substrate), the process can be fairly complex as different etch chemistries may be necessary to etch the different materials. Furthermore deep holes result in a high aspect ratio, which is difficult to obtain via etching and filling. In order to contact the via from the back side of the wafer further processing typically includes thinning the wafer substrate until the conductive layer in the TSV 10 is exposed.
An example of TSVs 10 processed through BEOL and FEOL as in FIG. 2 can be found in parts 3 and 4 of FIG. 3, before and after bonding and thinning, respectively. This figure is taken from an article by Steve Lassig, “Manufacturing integration considerations of through-silicon via etching”, in Solid State Technology, The international magazine for semiconductor manufacturing, December 2007.
In an alternative approach, via holes are etched or drilled from the wafer backside after first thinning the substrate (Proceedings of the 57th Electronic Components and Technology Conference, p 643). This approach is shown in FIG. 4. In this case the stack through which the hole needs to penetrate is considerably simpler and typically includes, or only consists of, the substrate 5, e.g. Si, and a dielectric stack 14, 13. An advantageous feature of this process flow is that it is much less dependent on the details of the stack built up on the front side of the wafer. The process therefore is much more generic and can be applied to a wide variety of devices. Implementation schemes for this approach will typically show vias landing on a metal pad, e.g. a Cu or Al metal pad, in the metal one M1 layer. A disadvantage of this approach is the fact that the etching of the TSVs stops in metal thereby increasing the risk of metal contamination of the tools. A further disadvantage is that an etch through the dielectric stack is needed, which is difficult if one does not know the stack, hence does not know the chemistry needed. This is an issue in particular when wafers have to be stacked which do not come from in-house or come from different sources/fabs.